1. Field of the Invention
The present invention relates to a digital PLL (Phase Locked Loop) circuit used in a frequency synthesizer, an FM demodulator, and the like.
2. Description of the Related Art
In such cases where digital data recorded on a recording medium such as a magnetic tape and a magneto-optic tape is reproduced, a reproduction clock is required for extracting reproduced data from information read from the recording medium. For example, a PLL circuit is used for generating a clock synchronous with such read information.
Forming a PLL circuit as an analog circuit has a problem of unstable operation under manufacturing variation and fluctuation in operating conditions (temperature, voltage, and so on) of semiconductor elements. In addition, since an analog circuit is larger in scale than a digital circuit, a circuit scale of the PLL circuit becomes larger. Therefore, the PLL circuit in recent years has come to be formed as a digital circuit. A digital PLL circuit of this kind is disclosed in, for example, Japanese Unexamined Patent Application Publication No. Hei 8-274629, and so on.
FIG. 1 shows a digital PLL circuit disclosed in Japanese Unexamined Patent Application Publication No. Hei 8-274629.
A digital PLL circuit 9 is composed of a phase comparator 1, a decoder 2, an output clock selection circuit 3, an oscillator 4, a clock generation circuit 5, a variable divider 6, a loop filter 7, and a frequency comparator 8.
The frequency comparator 8 detects a frequency error between a reference clock Sin and an output clock Sout to output frequency error signals. The loop filter 7 integrates the frequency error signals in order to prevent the influence by frequency jitter to output a control signal to the variable divider 6. The variable divider 6 frequency-divides a master clock outputted by the oscillator 4 at a division ratio in accordance with the control signal to output a divided master clock. Based on the divided master clock, the clock generation circuit 5 outputs a plurality of clocks having equally shifted phases. The phase comparator 1 detects a phase error between the reference clock Sin and the output clock Sout to output a phase error signal. The decoder 2 decodes the phase error signal to output an output clock selection signal. The output clock selection circuit 3 selects an optimum clock from the plural clocks outputted by the clock generation circuit 5, according to the output clock selection signal so as to minimize the phase error between the reference clock Sin and the output clock Sout and outputs the selected clock as the output clock Sout.
With the above-described configuration, the output clock Sout has a frequency and a phase that are adjusted so as to approximate the frequency and phase of the reference clock Sin respectively.
In the digital PLL circuit 9, the output clock Sout is generated by appropriately frequency-dividing the master clock generated by the oscillator 4. Therefore, the oscillator 4 has to generate the master clock having a frequency high enough to correspond to the frequency of the output clock Sout. Further, in the digital PLL circuit 9, the oscillator 4 and the variable divider 6 changing the frequency of the master clock outputted from the oscillator 4 are separately formed, resulting in an increase circuit scale.